The invention relates to a process for manufacturing integrated devices comprising microstructures and associated suspended electrical interconnections.
As known, integrated structures have been recently proposed formed from a semiconductor material body and comprising suspended masses connected to the rest of the wafer by support regions and electrical connection regions. Such microstructures are used to produce, for example, accelerometers and sensors of various types (gas, pressure etc.) and microactuators. Generally, electrical connection regions are buried and formed by polysilicon strips surrounded by two insulating layers or by conductive regions formed in the starting substrate.
Two examples of buried connections are shown in FIGS. 1 and 2 and will be described below, for a better understanding.
FIG. 1 shows a wafer 1 of semiconductor material comprising a substrate 2 of single-crystal silicon and an epitaxial layer 3. A suspended mass 4 (defining an accelerometer for example) comprising an electrical connection portion 5 at the bottom is formed inside the epitaxial layer 3. The electrical connection portion 5 is in direct electrical contact with a buried connection line 6, typically of multi-crystal silicon, which connects the suspended mass 4 to an epitaxial region 10. The suspended mass 4, the buried connection line 6, and the epitaxial region 10 have the same electrical conductivity type, N for example, whereas the substrate 2 has P-type conductivity, for example. The electrical connection line 6 extends on substrate 2 and is electrically isolated from it by a first oxide layer 11. A second oxide layer 12 also isolates the electrical connection line 6 from the epitaxial layer 3 except at the contact with the epitaxial region 10 and at the suspended mass 4, where the oxide layer 12 has been removed to free the suspended mass 4.
In the solution of FIG. 2 the buried connection line, now denoted by 15, is formed inside the substrate 2 to form a diode 16. In this solution the first oxide layer 11 is not present but the second oxide layer 12 may be present. By biasing the substrate 2 at a voltage that is always lower than the voltage of the suspended mass 4, and therefore lower than the buried connection line 15 (by connecting the substrate 2 to ground and the regions 4, 15 and 10 to a positive voltage, for example), the diode 16 is reverse-biased and defines a junction isolation.
The buried connections described above have many disadvantages mainly due, as regards the solution of FIG. 1, to inadequate breakdown voltage of insulating oxide layers 11 and 12, and as regards the solution of FIG. 2, possible losses of diode 16 towards the substrate 2 and possible triggering of parasitic components formed by adjacent connection lines and inadequate reverse breakdown voltage of diode 16. Furthermore, in both cases, the connection lines 6, 15 are exposed while etching the sacrificial layer to enable the suspended mass 4 to be freed.
Suspended connection lines also have been already proposed, but considerable problems have been encountered in producing them. In fact they cannot be produced at the end of the process, after the suspended mass has been freed. On the other hand, the excavation operations to free the suspended mass run the risk of damaging them.
An advantage of the invention is therefore to provide a manufacturing process to address the above problems.
An embodiment of the invention provides a process for manufacturing an integrated device and an integrated device thus produced, as defined in the claims.